1. Field of the Invention
Embodiments of the present invention relate generally to image sensors and methods and, in specific embodiments, to image sensors with control lines that provide control signals to pixels.
2. Related Art
Image sensors have found wide application in consumer and industrial electronics, and have enabled an explosion in a number of digital cameras and digital video devices used for work and entertainment.
FIG. 1 illustrates an architecture of a related art image sensor 1. The image sensor 1 includes a pixel array 2, a row driver 4, column readout circuitry 7, and a column circuit timing controller 9. The pixel array 2 includes pixels 3 that are arranged in rows and columns. Each pixel 3 includes a light sensitive element, such as a photodiode, or the like, to sample light intensity of a corresponding portion of a scene being imaged, and each pixel 3 is configured to produce an analog pixel signal based on the sampled light intensity. The row driver 4 supplies control signals to the pixels 3 in the pixel array 2 to control an operation of the pixels 3.
Pixels 3 that are in a same row of the pixel array 2 share common row control signals from the row driver 4. For example, pixels 3 in a first row of the pixel array 2 share common row control lines 51 for receiving control signals from the row driver 4. Similarly, pixels 3 in a second row of the pixel array 2 share common row control lines 52 for receiving control signals from the row driver 4, and pixels 3 in an nth row of the pixel array 2 share common row control lines 5n for receiving control signals from the row driver 4. Pixels 3 that are in a same column of the pixel array 2 share a common column readout line to provide output. For example, pixels 3 in a first column of the pixel array 2 share a column readout line 61, pixels 3 in a second column of the pixel array 2 share a column readout line 62, and pixels 3 in an mth column of the pixel array 2 share a column readout line 6m. The row driver 4 controls the pixels 3 to provide output row by row.
FIG. 2 illustrates an example of a conventional pixel 3. The pixel 3 illustrated in FIG. 2 is provided as an example of a pixel in a kth column of a pixel array, such as the pixel array 2 (refer to FIG. 1). The pixel 3 includes a substrate 20, a photodiode (PD) 21, a transfer gate 22, a storage diffusion 23, an anti-blooming gate 24, an anti-blooming gate diffusion 25, a reset transistor 26, a source follower transistor (SF) 27, and a row select transistor 28. The storage diffusion 23 may also be called a floating diffusion (FD) node 23 or a readout node 23. The anti-blooming gate 24 may also be called a shutter gate 24. The photodiode 21 may be, for example, a pinned photodiode that collects charge during exposure based on the light intensity of a corresponding portion of a scene being imaged.
The transfer gate 22 is connected to receive a transfer control signal (TX), and the transfer gate 22 is controllable by the transfer control signal TX to transfer charge from the photodiode 21 to the storage diffusion 23. The anti-blooming gate 24 is connected to receive an anti-blooming control signal (AB), and the anti-blooming gate 24 is controllable by the anti-blooming control signal AB to allow for charge to be drained from the photodiode 21 to the anti-blooming gate diffusion 25. The anti-blooming gate diffusion 25 is connected to a reset voltage source (not shown) that supplies a reset voltage (Vrst).
A first terminal of the reset transistor 26 is connected to the reset voltage source that provides the reset voltage (Vrst). A gate of the reset transistor 26 is connected to receive a reset control signal (RST). A second terminal of the reset transistor 26 is connected to the storage diffusion 23 and to a gate of the source follower transistor 27. The gate of the source follower transistor 27 is connected to the storage diffusion 23 and to the second terminal of the reset transistor 26. A first terminal of the source follower transistor 27 is connected to a voltage source (not shown) that supplies a voltage (Vdd).
A second terminal of the source follower transistor 27 is connected to a first terminal of the row select transistor 28. A gate of the row select transistor 28 is connected to receive a row select control signal (ROW). A second terminal of the row select transistor 28 is connected to a column readout line 6k for providing a pixel output signal (pout) for the pixel 3 on the column readout line 6k. Thus, the pixel 3 is controlled with the four control signals AB, TX, RST, and ROW, and the pixel 3 provides an output signal (pout).
If space allows, the anti-blooming gate diffusion 25 and a source terminal of the reset transistor 26 receive power from the reset voltage source (not shown) supplying the reset voltage Vrst, which can be run either horizontally, or vertically, or as a mesh in a pixel array. The source follower transistor 27 is powered from the voltage source (not shown) supplying Vdd, which is run as a vertical wire in each column of a pixel array. If space is tight, Vrst can be combined with Vdd.
FIG. 3 illustrates a circuit diagram representation of the pixel 3 of FIG. 2. In FIG. 3, the transfer gate 22 and the anti-blooming gate 24 are represented as gates of transistors, with a first terminal of each of those transistors connected to the photodiode 21. Those two transistors plus the reset transistor 26, the source follower transistor 27, and the row select transistor 28 equal five transistors, so the pixel 3 is conventionally referred to as a five transistor (5T) pixel. The floating diffusion node 23 is connected to the gate of the source follower transistor 27. The anti-blooming gate diffusion 25 is connected to a voltage source (not shown). The pixel 3 is connected to provide output on the column readout line 6k.
An operation of the pixel 3 is now described with reference to FIGS. 2 and 3. When the anti-blooming control signal AB applied to the anti-blooming gate 24 is HIGH, all charges from the photodiode 21 are drained out into Vrst or Vdd (whatever is connected to the anti-blooming gate diffusion 25). When an image capture operation is initiated for the pixel 3, the anti-blooming control signal AB and the transfer control signal TX are controlled to be LOW, so that charge is collected during exposure in the photodiode 21. Prior to transferring the charge, the floating diffusion node 23 is cleared either with a reset pulse by controlling the reset control signal RST to be HIGH and then LOW, or the floating diffusion node 23 remained empty from a previous readout from the floating diffusion node 23.
The transfer of charge from the photodiode 21 to the floating diffusion node 23 is then performed by controlling the transfer control signal TX applied to the transfer gate 22 to be HIGH. After the transfer is done, the transfer control signal TX is controlled to be LOW, and a new exposure in the photodiode 21 can start, controlled by the anti-blooming control signal AB. The anti-blooming control signal AB can be controlled to be HIGH to cause charge to be drained from the photodiode 21, and then exposure starts with bringing the anti-blooming control signal AB to LOW. The readout of charge from the pixel 3 is done in parallel with an exposure that collects charge for a subsequent readout.
The readout from the pixel 3 can start right after the transfer of the charge from the photodiode 21 to the floating diffusion node 23. The readout is performed row by row in the pixel array 2 (refer to FIG. 1). To perform the readout from the pixel 3, the row select control signal ROW is controlled to be HIGH, and a pixel signal corresponding to a charge at the floating diffusion node 23 is read out over the column readout line 6k. The row select control signal ROW is then controlled to be LOW, and the reset control signal RST is controlled to be HIGH to empty the floating diffusion node 23. The reset control signal RST is then controlled to be LOW and the row select control signal ROW is controlled to be HIGH to read out a potential (the reset value) of the empty floating diffusion node 23 over the column readout line 6k.
The pixel signal corresponding to the charge at the floating diffusion node 23 prior to reset and the reset value corresponding to the reset potential at the floating diffusion node 23 after reset are provided to a corresponding column readout circuit 8 (refer to FIG. 1) for the column in which the pixel 3 is located. The column readout circuit 8 digitizes a difference between the pixel signal and the signal of the reset potential to provide a digital output representing the charge collected by the pixel 3 during the corresponding exposure.
With reference again to FIG. 1, the column readout circuitry 7 includes a column readout circuit 8 for each column of pixels 3 in the pixel array 2. Each column readout circuit 8 is connected to receive analog signals from a corresponding column readout line, and is configured to provide digital output on a corresponding output line. For example, the column readout circuit 8 for the first column is connected to the column readout line 61 for receiving input, and is connected to an output line 111 for providing output. Similarly, the column readout circuit 8 for the second column is connected to the column readout line 62 for receiving input, and is connected to an output line 112 for providing output, and the column readout circuit 8 for the mth column is connected to the column readout line 6m for receiving input, and is connected to an output line 11m for providing output. The column circuit timing controller 9 is configured to provide control signals to the plurality of column readout circuits 8 over one or more control lines 10.
FIG. 4 illustrates a portion of the pixel array 2 (refer to FIG. 1) including a pixel 31 in a first row and a first column of the pixel array 2 (refer to FIG. 1) and a pixel 32 in a second row and the first column of the pixel array 2 (refer to FIG. 1). The pixel 31 and the pixel 32 have a structure that is the same as the pixel 3 (refer to FIGS. 2 and 3), and the subscripts in the labels for the pixels are merely provided to indicate the rows in which the pixels are located.
The row control lines 51 for the first row include a reset control line (rst1), a row select control line (row1), a transfer control line (tx1), and an anti-blooming control line (ab1). With reference to FIGS. 3 and 4, the transfer gate 22 of the pixel 31 is connected to receive a transfer control signal over the transfer control line tx1; the anti-blooming gate 24 of the pixel 31 is connected to receive an anti-blooming control signal over the anti-blooming control line ab1; a gate of the reset transistor 26 of the pixel 31 is connected to receive a reset control signal over the reset control line rst1; and a gate of the row select transistor 28 of the pixel 31 is connected to receive a row select control signal over the row select control line row1. The reset control line rst1, the row select control line row1, the transfer control line tx1, and the anti-blooming control line ab1 for the row control lines 51 are shared by all pixels in the first row of the pixel array 2 (refer to FIG. 1), and the control signals on those lines are provided from the row driver 4 (refer to FIG. 1).
The row control lines 52 for the second row include a reset control line (rst2), a row select control line (row2), a transfer control line (tx2), and an anti-blooming control line (ab2). The transfer gate 22 of the pixel 32 is connected to receive a transfer control signal over the transfer control line tx2; the anti-blooming gate 24 of the pixel 32 is connected to receive an anti-blooming control signal over the anti-blooming control line ab2; a gate of the reset transistor 26 of the pixel 32 is connected to receive a reset control signal over the reset control line rst2; and a gate of the row select transistor 28 of the pixel 32 is connected to receive a row select control signal over the row select control line row2. The reset control line rst2, the row select control line row2, the transfer control line tx2, and the anti-blooming control line ab2 for the row control lines 52 are shared by all pixels in the second row of the pixel array 2 (refer to FIG. 1), and the control signals on those lines are provided from the row driver 4 (refer to FIG. 1).
The anti-blooming gate diffusion 25, the first terminal of the reset transistor 26, and the first terminal of the source follower transistor 27 of the pixel 31 are connected to a power source (not shown) to receive a voltage (Vdd) over a voltage line (pvdd) 121. The anti-blooming gate diffusion 25, the first terminal of the reset transistor 26, and the first terminal of the source follower transistor 27 of the pixel 32 are also connected to the power source (not shown) to receive the voltage (Vdd) over the voltage line (pvdd) 121, which is a shared voltage line among all the pixels in the first column of the pixel array 2 (refer to FIG. 1).
The pixel 31 is connected to provide output on the column readout line 61. The pixel 32 is also connected to provide output on the column readout line 61, which is a shared column readout line among all the pixels in the first column of the pixel array 2 (refer to FIG. 1). The pixels 3 in the pixel array 2 (refer to FIG. 1) are controlled row by row to provide output, so the pixels 31 and 32, which are in different rows from each other, provide output on the column readout line 61 at different times from each other.
As was mentioned above, the pixel 3 of FIG. 3 is conventionally referred to as a five transistor (5T) pixel. Other types of pixels have also been used in various image sensors. For example, an embodiment of a four transistor (4T) pixel is illustrated in FIG. 2A of U.S. patent application Ser. No. 12/405,903, filed Mar. 17, 2009, and published as U.S. Patent App. Pub. No. 2009/0273696, the entire contents of which are incorporated by reference herein. The 4T pixel, which is also referred to as a 4T rolling shutter pixel, may include a pinned photodiode and may allow for achieving low noise through the implementation of true correlated double sampling. In addition to a photodiode, the 4T pixel further includes a transfer gate connected to receive a corresponding in-row transfer control, a sense node (also called a floating diffusion) where charge from the photodiode is transferred via the transfer gate, a reset transistor connected to receive a corresponding in-row reset control to reset the floating diffusion, and a source follower (also called an amplifier) that can output a voltage onto a common vertical readout line upon enablement of a row select switch by a corresponding in-row row select control. The source follower and the reset transistor of the 4T pixel can be powered from pixel Vdd.
In the 4T rolling shutter pixels, the voltages at the floating diffusions are measured (read out through the source follower) in a selected row just before transfer of charge from the photodiode and then measuring the transferred charge. Each transfer empties the photodiode and starts a new integration of charge at the photodiode. Because the readout is done row by row, transfer control signals are applied to the image array row by row, and the exposure time for every next row is shifted by one row time. Such a readout from the pixel array is referred to as a “rolling shutter,” meaning that the exposures are not simultaneous across the image array but rather are shifted with respect to the position of the row in the image. Measuring floating diffusion voltage before transferring the charge allows for removing KTC noise of the floating diffusion capacitor and achieves low readout noise. As a consequence, 4T rolling shutters have become popular in commercial image sensors such as image sensors used in cell phones.
A miniaturization of the 4T rolling shutter pixel was achieved through the sharing of readout circuitry, including the floating diffusion, the reset transistor, the source follower transistor, and the row select transistor, among neighboring pixels, such as sharing readout circuitry among two neighboring pixels in one row (horizontal sharing of readout circuitry) or among two neighboring pixels in one column (vertical sharing of readout circuitry) that are examples of 2-way share, or sharing readout circuitry among four nearby pixels (two vertical and two horizontal) that is an example of 4-way share. In the related art, when readout circuitry is combined between two pixels in different rows (vertical 2-way share or 4-way share), this removes one row control line and one reset control line for each two rows of pixels, so less control lines are needed to control the pixel array. There is still the requirement in the related art, however, to have separate transfer control lines for each row of pixels to have the ability to measure the charges from the individual photodiodes.
The rolling shutter operation discussed above is a type of shutter operation. Another type of shutter operation is a global shutter operation. Pixels that can be used for global shutter operations are called global shutter pixels. An example of a global shutter pixel is the 5T pixel illustrated in FIG. 3. In a global shutter operation, the transfer of charge from the photodiode of each pixel to the pixel storage of each pixel is done simultaneously for all pixels in the pixel array, so the exposure ends at a same time for all the pixels. The beginning of the exposure in the global shutter operation can be controlled, for example, by using a shutter or anti-blooming gate. In the 5T pixel, since the pixel storage is a floating diffusion, the pixel storages cannot be combined for neighboring pixels, because the storages keep the individual photodiode charges for a large portion of a frame time. As a consequence, the technique to share readout circuitry does not work for a 5T pixel, because the 5T pixel uses the readout node for storing charge for the shuttered signal and, thus, the readout node is individual to a particular pixel and cannot be shared with other pixels.